Conventional techniques to increase the levels of device integration on integrated circuit substrates can often lead to reductions in device yield and device reliability. Some of these reductions in device yield may be caused by the formation of voids or gaps within electrically insulating layers and also within electrical interconnects that may extend through one or more electrically insulating layers. In particular, the conformal deposition of relatively thick electrically insulating layers on closely-spaced integrated circuit structures having relatively narrow aspect ratios may lead to the formation of voids in the spaces between the integrated circuit structures. These voids can result in the formation of electrical shorts between electrical interconnects and other integrated circuit structures formed on the substrate. One attempt to address this problem includes the use of thinner insulating layers, however, the use of thinner insulating layers may lead to increases in parasitic capacitive coupling between adjacent integrated circuit structures, which can lower device operating speeds. Etch-back and other planarization techniques have also been developed to make the surface profiles of deposited insulating layers more uniform and limit the range of peaks and valleys in the surface profile. Unfortunately, such planarization techniques may not be effective when the layers to be planarized are located very close to a primary surface of an integrated circuit substrate.